However, all other driver control structure members should be considered read-only and should not be modified. See below, for an explanation of each MII flag. If these flags are not set then the speed is set using the SROM settings. Check the Intel web site for latest information. Again, see the device hardware reference manual for details. The driver uses this value to program register CSR6. If this routine is called with an empty but allocated string, it puts the name of this device that is, “dc” into the initStr and returns 0.
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Again, see the device hardware reference manual for details.
If these flags are not set then the speed is set using the SROM settings. By default, the driver sets the Ethernet chip into a non-polling mode.
DEC PCI Board Generalities
As input, this function expects a string of colon-separated parameters. In such cases, all the registers which the chip DMAs to have to be swapped and written to, so that when the hardware swaps the accesses, the chip would see them correctly.
If this is specified as NONE -1the default of 32 lci used. It can also be used to review the ROM contents itself.
This controls how much data the device can absorb under load. However, the user may wish to force the PHY to negotiate its technology abilities a subset at a time, and according to a particular order.
The driver control structure member mediaCountis initialized to 0xff at startup, while the other media control members mediaDefaultmediaCurrentand gprModeVal are initialized to zero. Transmission starts oci the frame size within the transmit FIFO is larger than the treshold value.
It is used to translate a physical memory address into a PCI-accessible address. The supports HomePNA 1.
This driver is designed to be moderately generic. No jumpering diagram is necessary. All of the device-specific parameters are passed in the initStr. This routine should reset, initialize, and select an appropriate media. However, all other driver control structure members should be considered read-only and should not be modified.
Pcj processors can be connected to the PCI bus through some controllers that take care of hardware byte swapping. Although PCI configuration for a device is handled in the BSP, all other device programming and initialization needs are handled in this module. This should be selected taking into account the actual operating speed of the PHY. A media select routine is typically defined as: In which case, the driver allocates cache safe memory for its use using cacheDmaAlloc.
On thethe driver configures the 10BASE-T interface by default,waits for two seconds, and checks the status of the link. It does not signify the end of the original string, but that the parameter is null.
The module that is responsible for optimally configuring the media layer will start scanning the MII bus from the address in phyAddr. Alternatively, the chip can be programmed to poll for the next available transmit descriptor if the transmit engine is in idle state. The parameters pcci be specified as hexadecimal strings optionally preceded by “0x” or a minus sign “-“. This routine can use these fields in any manner.
Check the Intel web site for latest information.
Without modification, it can operate across the full range of architectures and 221140 supported by VxWorks. The 2 bytes of data are extracted and processed into a normal pair of bytes. If any of the assumptions stated below are not true for your particular hardware, you need to modify the driver before it can operate correctly on your hardware.
The driver also and contains error recovery code 211140 handles known device errata related to DMA activity. The driver uses this value to program register CSR6.